1. Field of the Invention
The present invention relates to a semiconductor assembly, and more particularly to a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole and dual build-up circuitry.
2. Description of Related Art
In the field of electronic systems, there is a continuous need to improve performance and reduce size and weight. Many approaches have been proposed to meet these requirements and strike a balance between performance optimization, time-to-market expedition and cost reduction through the use of different architectures, materials, equipment, process nodes, and manufacturing methods. Among all efforts, technical innovations at packaging-level are considered the most cost effective and least time consuming. Furthermore, as there are significant obstacles to further reduce chip feature sizes below the nanometer range due to significant expense for material, equipment and process developments, attention has therefore shifted to packaging technologies to timely fulfill the relentless demands for a smarter and smaller device.
Plastic packages such as ball grid array (BGA) or QFN (Quad Flat No-Lead) commonly contain one chip per package. In order to accommodate more functions and minimize signal delay, stacking multiple chips in a package to reduce the length of interconnection and maintain minimal footprint has become promising. For instance, stacking a mobile-processor die with a separate memory chip can enhance device speed, footprint, and power consumption. Furthermore, stacking multiple chips in a module allows accommodating different function chips including logic, memory, analog, RF, integrated passive component (IPC) and micro-electrical mechanical systems (MEMS) at different process nodes, such as 28 nm for high-speed logic and 130 nm for analog.
Despite numerous three-dimensional packaging architectures reported in the literature, many performance-related deficiencies remain. For instance, multiple devices stacked in a limited space often encounter undesirable inter-device noise such as electromagnetic interference (EMI). The signal integrity of the stacked devices can be adversely affected when they perform high frequency transmitting or receiving of signals. Furthermore, as semiconductor devices are susceptible to performance degradation and immediate failure at high operating temperatures, collective heat generated from the chips enclosed in a thermally insulating material such as dielectrics can cause catastrophic damage to the assembly. As such, providing a stackable semiconductor assembly that can resolve electromagnetic interference, facilitate heat dissipation yet maintain low cost in manufacturing would be highly desirable.
U.S. Pat. No. 5,111,278 to Eichelberger discloses a multi-chip module that is three dimensional stackable. In this approach, semiconductor chips are disposed on a flat substrate and sealed by an encapsulant with via openings formed on the connection pads. A pattern of conductors disposed on the encapsulant extend to the exposed bonding pads and thus interconnect these semiconductor chips from the upper surface of the module. Plated through-holes are deployed in the module to connect upper and lower circuitries and thus establish the three-dimensional stacking for the embedded chips. However, as most plastic material has low thermal conductivity, this plastic assembly suffers poor thermal performance and offers no electromagnetic shielding protection for the embedded chips.
U.S. Pat. No. 5,432,677 to Mowatt et. al., U.S. Pat. No. 5,565,706 to Miura et al., U.S. Pat. No. 6,680,529 to Chen et al. and U.S. Pat. No. 7,842,887 to Sakamoto et al. disclose various embedded modules to address manufacturing yield and reliability concerns. None of these approaches offers a proper thermal dissipation solution or effective electromagnetic protection for the embedded chips.
U.S. Pat. No. 7,242,092 to Hsu and U.S. Pat. No. 7,656,015 to Wong disclose an assembly in which the semiconductor chip is housed in a cavity with a bottom metal layer in the cavity to facilitate heat dissipation for the embedded chip. Since the cavity in the substrate is formed by laser or plasma etching of the substrate, the major drawbacks include low throughput and high cost in forming the cavity in addition to the limited heat dissipation capability of the bottom metal layer in the structure.
U.S. Pat. No. 7,777,328 to Enomoto discloses a thermally enhanced assembly in which a cavity for the die placement is formed by micro-machining or by milling out a portion of a metal. Inconsistent cavity depth control of the recess in the metal plate can result in low throughput and low yield in volume production. Furthermore, as the thick metal plate would electrically block the vertical connection to the bottom surface, resin filled holes need to be created before metallized plated through-holes can be built in the metal block. The cumbersome process makes the manufacturing yield excessive low and costly.
U.S. Pat. No. 7,957,154 to Ito et al. discloses an assembly in which a metal layer is formed on the inner wall surface of a cavity so that the embedded semiconductor chip can be protected from electromagnetic interference. Like many other cavity type approaches, this assembly suffers poor manufacturing throughput and low yield due to inconsistent cavity formation in the resin. Furthermore, since the metal is deposited in the cavity by electroplating, it has limited thickness and does little to improve the package's thermal performance.
In view of the various development stages and limitations in currently available packages for high power and high performance semiconductor devices, there is a need for a semiconductor assembly that is cost effective, reliable, manufacturable, versatile, provides good signal integrity and has excellent heat spreading and dissipation.